1. Field of the Invention
The present invention relates to a high speed and low power D/A converter, and in particular to a high speed and low power D/A converter which is capable of accurately outputting an analog value and implementing a high speed operation by reducing noise and errors which occur during a code conversion.
2. Description of the Conventional Art
FIG. 1 illustrates the construction of a conventional 8-bit CMOS D/A converter which includes a column decoder 1 and a row decoder 2 receiving predetermined bit signals among 8-bit input signals, and a cell plate (matrix array) 3 having a plurality of current cells and outputting a predetermined level of current in accordance with the output signals from the column decoder 1 and the row decoder 2.
Here, each current cell is composed of a logic gate and a current source. The current level outputted by each current cell is identical (equally weighted).
The operation of the conventional 8-bit CMOS D/A converter will now be explained with reference to FIG. 1.
First, when 8-bit (B0-B7) digital signals are inputted, the column decoder 1 and the row decoder 2 decode predetermined bit signals among the 8-bit input signals for thus turning on the current sources of the current cells. When the current from the turned-on current sources flows through an externally connected load resistor R, an analog output voltage Vout is outputted in a voltage-dropped form.
Thus, in the case of converting 8-bit signals, it is possible to implement a total of 2.sup.8 =256 discrete current levels.
When the current cells are equally weighted, namely, when the current cell plate 3 is composed of segmented cells, the current cells of the cell plate 3 are sequentially selected by adjusting the 8-bit input value, and then the current levels flowing from the selected current cells are combined, so that the amount of current outputted is monotonically increased from the 1st level to the 256th level. As a result, whenever one current cell is turned on, the currents from the current source are combined, so that it is possible to obtain an analog signal level which ranges from 1 to 256 steps.
When the current cells are differently weighted, namely, the current cells are weighted in steps of 1, 2, 4, 8, 16, . . . , n, the current cells are not sequentially turned on. Namely, the appropriately weighted current cells are selected for thus implementing a corresponding level.
Namely, in order to implement an analog level of 32, only the current cells corresponding to analog output level of 32 are turned on, and the other current cells are all turned off, for thus implementing an appropriate level output.
The conventional D/A converters have various problems, among is in providing a monotonic characteristic, namely, that as the digital value is increased, the analog value must correspondingly steadily increase.
In other words, the monotonic characteristic means that as a digital information value is gradually increased, the analog value is gradually increased without any decrease or nonlinearity. Therefore, when the DIA converter is used in a display system such as a digital television or a high definition television, the monotonic characteristic is a very important factor. In order to obtain a good monotonic characteristic, a desired linear characteristic must be obtained when converting digital signals into analog signals.
When configuring the current cells of the cell plate 3 using segmented cells, since the current cells are turned on one by one in order to obtain a predetermined analog level, it is possible to obtain a monotonic characteristic. However, the configuration and coding operation of the current cells become complicated, the power consumption is increased, and the conversion speed of the circuit is decreased.
In addition, when configuring the current cells of the cell plate 3 using weighted cells, the coding operation and cell configuration are more easily implemented. However, it is difficult to obtain a desired monotonic characteristic.
Therefore, the segmented cells and the weighted cells are used together in order to overcome the above-described problems. In this case, as the number of bits of the D/A converter is increased, the role of the weighted cells is increased. Therefore, it becomes still difficult to obtain a desired monotonic characteristic.
The second problem is in that much noise may be generated during code conversion.
When a digital value is increased by one binary digit, for example, the binary value to be converted changes from 01111111 into 10000000, as the binary value is changed from 0 to 1 or from 1 to 0 at each digit position, a discontinuity problem occurs due to noise which is generated during a short time.
Furthermore, since the D/A converter is operated at about 100 MHz or higher, such noise increases a delay time, which is required until a stable analog signal level is obtained, namely, a settling time, thus limiting the data conversion speed.